Fly-by direct memory access (“DMA”) read and write operations are employed to free up valuable system resources such as a central processing unit (“CPU”) and DMA controller from having to extensively manage data transfers between a memory and PCI-bus. An example of such fly-by DMA operation is described in U.S. patent application Ser. No. 09/888,321 entitled “Transaction Aligner Microarchitecture” filed Jun. 21, 2001, assigned to the same Assignee as the present invention, and incorporated herein in its entirety by this reference.
Management of data transfers between a memory and a PCI-bus can be complicated, however, for a number of reasons. Although it may be desirable to manage certain functions on a byte-at-a-time basis, data transfers on the memory's bus and the PCI-bus typically use word addresses so that data are transferred on a word-at-a-time basis. Each word typically comprises multiple bytes to form multi-byte words. Valid data for multi-byte words may start and end at arbitrary byte locations in the multi-byte words. Data aligners are commonly employed since the starting and ending byte locations may be different for data communicated from and to the memory and data communicated from and to the PCI-bus. Data communicated to and from the PCI-bus may also require swapping between big and little Endian orientations. To simplify implementation, a fixed byte enable vector may be required to be provided during each burst transfer of data to the PCI-bus. Also, data transfer rates from and to the memory may not be related to data transfer rates from and to the PCI-bus.